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The present invention relates generally to etching trenches in substrates, and more specifically to a method of etching deep trenches in substrates that allows precise control of lateral undercut. The present invention also relates to a method of fabricating on-chip devices and micro-machined structures using the deep trench etching method.
Trenches are frequently etched in substrates to form micro-electromechanical devices, to form micro-machined structures such as cantilevers or optical mirrors, and to reduce electromagnetic coupling and parasitic capacitance between on-chip devices and the substrate. Such applications in which either an on-chip device or micro-machined structure is suspended over a trench etched in a substrate present unique challenges for semiconductor manufacturers. This is because trench etching equipment has traditionally been used for either highly anisotropic etching or highly isotropic etching of substrates. In general, such highly anisotropic or isotropic etching cannot provide precise, controlled removal of substrate material located underneath on-chip devices and micro-machined structures.
One approach to fabricating on-chip devices is described in a publication entitled A Universal MEMS Fabrication Process for High-Performance On-Chip RF Passive Components and Circuits, Jiang et al., Solid-State Sensor and Actuator Workshop, June 2000. According to that fabrication process, silicon nitride is deposited and patterned on the substrate surface as an isolation layer, a trench is etched in the substrate by deep reactive ion etching, and a sacrificial silicon-oxide block is formed in the trench and on the isolation layer. Next, an on-chip device suspended over the trench is built by polysilicon surface micro-machining and released in hydrofluoric acid, and copper plating is performed. However, one drawback of the process of Jiang et al. is that it includes many complicated steps that can significantly increase costs of manufacture.
One approach to fabricating a micro-machined structure such as a cantilever is described in U.S. Pat. No. 6,086,774 issued to Ho et al. According to that fabrication process, a cantilever is formed by performing two (2) etching steps at opposing, non-normal angles to the substrate surface. The respective etching angles and depths are chosen such that the etched region completely undercuts and releases a portion of the substrate. Unetched substrate material under the released structure is then removed by exposing the reverse side of the substrate to a backside etch. However, the process steps described by Ho et al. are also complicated and can lead to higher manufacturing costs. Further, the process of Ho et al. can become increasingly difficult to use as die sizes are reduced and/or wafer sizes are increased. For example, as the thickness of a wafer increases, it generally becomes more difficult to perform a backside etch of the substrate.
Still another fabrication process is described in U.S. Pat. No. 4,600,934 issued to Aine et al. According to that fabrication process, an etch resistant layer is deposited on the substrate surface, angled notches are formed in the etch resistant layer, and anisotropic undercut etching is performed in the region of the notches. The rate of undercut etching is determined by the angle of the notches relative to the crystal planes of the substrate. However, the process steps described by Aine et al. are also complicated and can lead to increased manufacturing costs.
It would therefore be desirable to have a method of etching a trench in a substrate that can be employed to remove substrate material located underneath on-chip devices and micro-machined structures. Such a method would allow precise control of lateral undercut, provide increased yields, and reduce manufacturing costs.
In accordance with the present invention, a method of etching a deep trench in a substrate is provided that allows precise control of lateral undercut. The method includes the steps of optionally forming at least one on-chip device or micro-machined structure on a surface of a silicon substrate, and covering the surface with a masking layer such as photoresist, polyimide, metal, or oxide. A trench pattern is then imaged in or transferred to the masking layer such that a trench subsequently etched in the substrate according to the pattern at least partially surrounds the optionally formed on-chip device or micro-machined structure. In the event an on-chip device is formed in a device layer of the silicon substrate, the device layer is etched using a standard passivation etch technique to expose at least a portion of the bulk silicon. Upper portions of the trench are then anisotropically etched in the silicon substrate using a dry plasma etch technique. In a preferred embodiment, C4F8 and SF6 are employed as the active etching agents. Next, the trench is semi-anisotropically etched in the substrate with the C4F8 and SF6 active etching agents such that etching conditions are unchanged for the C4F8 anisotropic etching agent, but the etching conditions are modified for the SF6 isotropic etching agent. In a preferred embodiment, the etching conditions of the SF6 isotropic etching agent are modified to increase the pulse duration. The trench is then isotropically etched in the substrate with the SF6 isotropic etching agent. In a preferred embodiment, the bias power is reduced to a minimum during the isotropic etch. Finally, the remaining masking layer is stripped away. By modifying isotropic etching time, a precise, controlled lateral undercut can be achieved as the trench is etched vertically in the silicon substrate. Such a precise, controlled lateral undercut can be used to remove substrate material located underneath the on-chip device or micro-machined structure.
Other features, functions, and aspects of the invention will be evident from the Detailed Description of the Invention that follows.